1. Field of the Invention
The invention relates to an SOI wafer which comprises a silicon substrate, an electrically insulating layer with a high thermal conductivity and a silicon layer with a low defect density and high layer thickness homogeneity, and to a process for producing the SOI wafer.
2. The Prior Art
SOI wafers (Silicon On Insulator) generally comprise three layers: on the front surface of a silicon wafer, which forms the bottom layer, there is firstly an electrically insulating layer, for example of silicon dioxide. In turn, on the electrically insulating layer there is a thin single-crystal silicon layer, in which the electrical components are subsequently fabricated. However, SOI wafers with just two layers are also known. These comprise an electrically insulating substrate, for example glass or sapphire, and a thin silicon layer. For component fabrication in the line widths which are expected in the future, in particular for the fully depleted technology (in which the depletion zone of the transistors is equal to the thickness of the single-crystal silicon layer), the single-crystal silicon layer will need to be very thin, i.e. to have a thickness of 0.1 μm or less.
The insulating layer of silicon dioxide which is customarily used has the drawback of a low thermal conductivity of just approx. 1.40 W/(Km). The heat which is generated during switching of the components therefore cannot be dissipated downward to a sufficient extent, resulting in the formation of areas with locally high temperatures (known as hot spots). These hot spots reduce the conductivity of the components, their maximum possible clock rate and their long-term stability or reliability.
Therefore, numerous efforts have been made to allow the use of electrically insulating materials of higher thermal conductivity for the SOI technology. By way of example, sapphire (aluminum oxide, Al2O3) can be used as substrate material for the thin silicon layer (Silicon On Sapphire, SOS). The thermal conductivity of α-aluminum oxide, at 30 W/(Km), is well above that of silicon dioxide. The drawbacks of this structure, in addition to its complex production, are the fact that the lattice constants of silicon and sapphire differ by approx. 10% and also the difference in the coefficient of thermal expansion (Si: 3.8·10−8/K; Al2O3: 9.2·1031 8/K). For example in the heteroepitaxy process, this leads not only to contamination and autodoping effects from aluminum, but also to crystallographic defects (dislocations, twinning, stacking faults), which can only be partially eliminated in a subsequent thermal annealing step. Vertical film inhomogeneities and lateral stresses at the silicon-aluminum oxide interface lead to a drop in charge carrier mobilities. Therefore, SOS is not used in ultrafast microelectronics, but rather for radiation-resistant applications. A further drawback consists in the fact that the silicon layer cannot be electrically influenced from below, since the substrate consists of the electrically insulating aluminum oxide over its entire thickness.
SOI wafers with three layers, comprising a substrate formed from a semiconducting material, an electrically insulating layer and a layer of semiconducting material above the electrically insulating layer, do not have the latter drawback.
JP01-315129 has described an SOI wafer of this type, which comprises a silicon substrate, an insulating layer of aluminum oxide and a thin silicon layer. JP03-069144 and JP03-069145 describe the production of an insulating layer of magnesium aluminum oxide (Spinell, MgAl2O4), on a silicon substrate. JP09-162088 discloses that α- and Υ-aluminum oxide (Al2O3), magnesium aluminum oxide (MgAl2O4), cerium oxide (CeO2) and calcium fluoride (CaF2) can be used as an insulating layer between a silicon substrate and a thin silicon layer. The insulating layer is produced on a silicon substrate by low pressure chemical vapor deposition (LPCVD) or molecular beam epitaxy (MBE) . Then, a silicon layer is deposited epitaxially on the insulating layer. Alternatively, the silicon layer can also be produced by joining a further silicon wafer to the insulating layer and then setting the desired layer thickness by grinding and polishing.
SOI wafers in accordance with the prior art documents cited, however, are of only limited suitability for the fabrication of electronic components, such as microprocessors, memory components for laptops or chips for telecommunications applications, since they give a low yield during the fabrication of electronic components.